Integrated semiconductor photonic circuits are used as parallel optical transceivers for high speed optical interconnect, and there is now the possibility to scale the capacity of the optical interconnect to 100 Gbps and beyond. The reach of such an interconnect may be up to a few tens of kilometers. The integration level of photonic circuits may be scaled by introducing many optical processing circuits onto a small chip of a few square millimetres in size, for example for use in emerging optical transport applications for mobile front-haul and back-haul networks and for use in optical circuit switching for data centres. These circuits may use complementary metal-oxide-semiconductor (CMOS) technology photonics.
These applications may utilise multi-wavelength technology, and wavelength division multiplexing (WDM) is often exploited to reduce the size of the chips housing such integrated semiconductor photonic circuits and to also reduce the number of input/output ports required on these chips.
The transmission of high speed WDM signals among semiconductor photonic chips interconnected in an optical network may require the semiconductor photonic circuits to be interfaced with standard single mode fibers (SMFs). The length of a section of SMF could be between 100 m to 10 Km.
Transmission of optical signals through an SMF makes those optical signals vulnerable to polarization mode dispersion (PMD). PMD is a random phenomenon which is caused by randomly varying birefringence of the SMF, which causes changes in the polarization modes of the optical signal being transmitted. This causes interfacing issues at the semiconductor photonic circuits. Existing solutions may utilise polarization diversity structures placed at the input of the semiconductor photonic chips, for example as described by Chao Li, Jing Zhang, Jeong Hwan Song, Huijuan Zhang, Shiyi Chen, Mingbin Yu and G.Q Lo “Semiconductor Polarization Diversity Optical Tunable Filter Circuits with Fiber Assembly” Proceedings of 2011 IEEE Micro-Wave Photonics. This solution results in increased chip area, increased complexity, higher losses and/or higher manufacturing and implementation cost.
Aspects and embodiments were conceived with the foregoing in mind.